Commonly known matrix display devices are, for example, a liquid crystal display device including an active matrix substrate, on which TFTs (Thin Film Transistors) are formed, and driver ICs (Integrated Circuits) for driving the TFTs.
FIG. 6 illustrates a TFT active matrix liquid crystal display device 101. The liquid crystal display device 101 is provided with a gate driver 102 and a source driver 103. The gate driver 102 is a circuit for driving rows of a matrix, and the source driver 103 is, a circuit for driving columns of the matrix.
On a transparent substrate, a plurality of gate lines Gn, Gn+1, . . . (hereinafter denoted by a reference sign G, when collectively termed) and a plurality of source lines Sn, Sn+1, . . . (hereinafter denoted by a reference sign S, when collectively termed) are formed so as to orthogonally intersect with each other. The plurality of gate lines G are driven by the gate driver 102 and the plurality of source lines S are driven by the source driver 103. In a position at each of intersections of the gate lines G and the source lines S, a pixel PIX is provided. The pixel PIX includes a TFT 104, a liquid crystal 105, and a storage capacitor 106. In each of areas surrounded by the gate lines G and the source lines S, a pixel electrode 107 (FIG. 7) is formed. The pixel electrode 107 serves as one electrode of the liquid crystal 105 and one electrode of the storage capacitor 106, and is connected to a drain electrode of the TFT 104. In a pixel PIX in an n-th row and in an n-th column, a source electrode of the TFT 104 is connected to a source line Sn in the n-th column, and a gate electrode of the TFT 104 is connected to a gate line Gn in the n-th row.
When a relationship between the gate lines and the pixel electrodes 107 is spotlighted in the liquid crystal display device 101 in which the pixels PIX are thus formed, it is recognized that the liquid crystal display device 101 in FIG. 6 is a so-called below-pixel-electrode gate type liquid crystal display device in which the gate line Gn in the n-th row is provided below the pixel electrode 107 in the n-th row. Further, as illustrated in FIG. 7, between the pixel electrode 107 and the gate line Gn and between the pixel electrode 107 and the gate line Gn−1, parasitic capacitances Cgd1 and Cgd2 are generated, respectively. In regard to the pixels in the first row, a gate line G0, which corresponds to the foregoing gate line Gn−1 for the pixels PIX in the n-th row, is not provided, so that a parasitic capacitance corresponding to the foregoing parasitic capacitance Cgd2 is not generated. FIG. 6 illustrates a difference between an equivalent circuit of a pixel in the first row (line G1) in which the parasitic capacitance Cgd2 is not generated and an equivalent circuit of a pixel in each of the second and subsequent rows (Gn (n≠1)) in which both the parasitic capacitances Cgd1 and Cgd2 are generated.
In the meantime, as illustrated in FIG. 8, a gate signal having an amplitude of Vgpp is sequentially applied to each gate line G. This gate signal varies a drain level of the TFT 104. That is, in each of the pixels PIX in the n-th row, via the parasitic capacitance Cgd2, the gate signal of the gate line Gn−1 varies the drain level of the TFT 104 by ΔV2, and via the parasitic capacitance Cgd1, the gate signal of the gate line Gn varies the drain level of the TFT 104 by ΔV1. Here, provided that the capacitance of the liquid crystal of the pixel PIX is denoted by Clc and the storage capacitance is denoted by Ccs, the above-mentioned ΔV2 and ΔV1 can be expressed as follows:ΔV1=Vgpp×{Cgd1/(Clc+Ccs+Cgd1+Cgd2)}ΔV2=Vgpp×{Cgd2/(Clc+Ccs+Cgd1+Cgd2)}
The ΔV1 produced by the gate signal of the gate line Gn of the n-th stage causes a center value Vcom of an amplitude of the drain level of the TFT 104 to be lower than a center value Vsc of an amplitude of a source signal by ΔV1. The ΔV2 produced by the gate signal of the gate line Gn−1 of the preceding stage raises an effective value of a voltage applied to the liquid crystal 105.
As described above, each of the pixels PIX in the first row is not provided with the gate line G0 that is a preceding stage which forms the parasitic capacitance. Cgd2. For this reason, the ΔV2 does not occur. Consequently, the effective value of the voltage applied to the liquid crystal 105 only in the pixels PIX in the first row becomes lower than the effective values supplied to the respective pixels PIX of the remaining rows. Due to this difference of the effective values, brightness of the pixels PIX only in the first row appears different in display from brightness of the remaining pixels PIX in a case where a driving condition of the display device deteriorates, for example, in a case where the value ΔV2 is large or in a case where a temperature becomes too high or low. For instance, when normally white liquid crystal is adopted, the first line appears a bright line.
In order to solve the above problem, various techniques have been conventionally proposed. For example, Patent Literature 1 discloses a liquid crystal display device in which a below-pixel-electrode gate type panel is provided with a dummy gate line (dummy line G0) in the vicinity of pixels of the first row. This dummy gate line is not involved in displaying but compensates the aforementioned asymmetry between the pixels of the first row and the remaining pixels. FIG. 9 is a circuit diagram illustrating a configuration of the liquid crystal display device according to Patent Literature 1. FIG. 10 is a timing chart of signals inputted into the dummy line and the gate lines of the liquid crystal display device of Patent Literature 1.
As shown in FIG. 9, in the liquid crystal display device of Patent Literature 1, the dummy line G0 for producing capacitances is arranged on an outer side of a gate line (i.e., in the example shown in FIG. 9, a top gate line) G1 located at an outermost position from which scanning by use of a scanning signal starts. The dummy line G0 is arranged to be parallel to the gate line G1, and to face the gate line G1 so that a pixel electrode 6 connected to a TFT 5 connected to the gate line G1 is between the dummy line G0 and the gate line G1.
With this configuration, the pixel electrode 6 connected to the TFT 5 connected to the top gate line G1 is located between the dummy line G0 above and the gate line G1 below. Consequently, all of the pixels are geometrically symmetrical in a vertical direction. Therefore, the pixels driven by the top gate line G1 have completely the same conditions as the pixels driven by the other gate lines G2, G3, . . . . Consequently, in a case of a normally white liquid crystal, for example, it is possible to restrain such a conventional phenomenon that a line of pixels in the top row appears a bright line or the like.
However, the above conventional technique 1 has a problem in that it is necessary to provide a dummy line. This results in an increase in the number of wirings and accordingly an increase in the circuit area. This is against a recent trend of decreasing cost, weight and thickness of liquid crystal displays.
In the meantime, Patent Literature 2 discloses a method according to which a dummy line G0 driving signal is generated in a mode in which display timing is controlled by a data enable signal in a liquid crystal display device. FIG. 11 is a plane view schematically illustrating a configuration of a gate driver of the liquid crystal display device according to Patent Literature 2. FIG. 12 is a timing chart of signals that are involved in timing control.
As illustrated in FIG. 11, a liquid crystal display panel 3 of the liquid crystal display device includes 768 gate lines G1, G2, . . . , and G768 connected to respective effective pixels. Furthermore, a dummy line G0, which serves as a dummy gate line, is provided in a stage preceding the gate line G1. In order to drive these 769 gate lines, a gate driver 2 includes cascade-connected three driver ICs each of which has 258 output terminals.
In the above configuration, a control IC generates a gate start pulse signal GSP and a gate clock signal GCK based on a data enable signal ENAB and a clock signal CK, respectively, with reference to timing of inputting the data enable signal ENAB. Then, the control IC supplies these generated signals to the gate driver 2 so that, before a source driver starts to output a write signal corresponding to display data of the first horizontal period in one vertical period, the gate driver 2 outputs a gate signal to a top output terminal OG0. Thus, on the occasion of performing display in the data enable mode, it is possible to drive the dummy line G0 before the write signal of the first horizontal period is outputted to a source line S.
In this way, the liquid crystal display device of Patent Literature 2 uses only the data enable signal but does not use horizontal and vertical synchronization signals, for generating liquid crystal driving signals. In consequence, it is possible to reduce the number of wirings for input signals.